Program

DIMES'24 took place in Room 615B of Hilton Austin.

The workshop proceedings are available in the ACM Digital Library. The individual papers and presentation slides are linked below.

Schedule

09:00 am — Welcome

09:05 am — Keynote: Data, Storage, Memory, and Overall System Efficiency
Gustavo Alonso (ETH Zurich)

09:50 am — Session 1: Let the Numbers Do the Talking – Benchmarks and Models (Chair: Timo Hönig)

• Performance Models for Task-based Scheduling with Disruptive Memory Technologies
  Birte Friesel, Marcel Lütke Dreimann, Olaf Spinczyk (Universität Osnabrück)
  Slides
• Demystifying Intel Data Streaming Accelerator for In-Memory Data Processing
  André Berthold, Constantin Fürst, Antonia Obersteiner, Lennart Schmidt, Dirk Habich, Wolfgang Lehner, Horst Schirmeier (Technische Universität Dresden)
  Slides

10:30 am — Discussion with Speakers from Session 1

10:45 am — Coffee Break

11:00 am — Session 2: There Must Be Order – Memory and Caches (Chair: Frank Bellosa)

• To Keep or Not to Keep - The Volatility of Replacement Policy Metadata in Hybrid Caches
  Nils Wilbert, Stefan Wildermann, Jürgen Teich (Friedrich-Alexander-Universität Erlangen-Nürnberg)
  Slides
• Moses: Heap Partitioning for Semantic Data Tiering
  Felix Eberhardt (IBM Research & Development Germany, Hasso Plattner Institute, University of Potsdam); Andreas Grapentin, Sven Köhler, Felix Grzelka (Hasso Plattner Institute, University of Potsdam); Timo Hönig (Ruhr University Bochum); Andreas Polze (Hasso Plattner Institute, University of Potsdam)
  Slides
• The New Costs of Physical Memory Fragmentation
  Alexander Halbuer, Illia Ostapyshyn (Leibniz Universität Hannover); Lukas Steiner (Rheinland-Pfälzische Technische Universität Kaiserslautern-Landau); Lars Wrenger (Leibniz Universität Hannover); Matthias Jung (Universität Würzburg and Fraunhofer IESE); Christian Dietrich (Technische Universität Braunschweig); Daniel Lohmann (Leibniz Universität Hannover)
  Slides

12:00 pm — Discussion with Speakers from Session 2

12:15 pm — Lunch

01:00 pm — Keynote: Realistic Expectations for CXL Memory Pools
Daniel S. Berger (Microsoft Azure & University of Washington)

01:45 pm — Session 3: A Silver Lining? – CXL Systems (Chair: Andreas Polze)

• Lupin: Tolerating Partial Failures in a CXL Pod
  Zhiting Zhu (Lepton AI Inc.); Newton Ni, Yibo Huang (The University of Texas at Austin); Yan Sun (University of Illinois Urbana-Champaign); Zhipeng Jia (Google LLC); Nam Sung Kim (University of Illinois Urbana-Champaign); Emmett Witchel (The University of Texas at Austin)
  Slides
• Fundamental OS Design Considerations for CXL-based Hybrid SSDs
  Daniel Habicht, Yussuf Khalil, Lukas Werling, Thorsten Gröninger, Frank Bellosa (Karlsruhe Institute of Technology)
  Slides

02:25 pm — Discussion with Speakers from Session 3

02:40 pm — Short Break

02:50 pm — Panel Discussion
Gustavo Alonso (ETH Zurich), Daniel S. Berger (Microsoft Azure & University of Washington), Philip Levis (Stanford), Andreas Polze (HPI, University of Potsdam), Emmett Witchel (The University of Texas at Austin)

03:35 pm — Coffee Break

04:00 pm — Session 4: Cards on the Table — Demos

• Novel Memory Technologies for Multi-Tenant Exploratory Programming
  Felix Grzelka, Sven Köhler, Andreas Polze (Hasso Plattner Institute, University of Potsdam)
  Slides

04:20 pm — Best Paper Award & Closing Remarks

Keynotes

Realistic Expectations for CXL Memory Pools

Daniel S. Berger (Microsoft Azure and University of Washington)

CXL promises increased memory bandwidth/capacity and cross-node pooling and sharing. While the CLX standard enables many possibilities and inviting configurations, systems research directions depend on what is realistic and can be deployed in datacenters. Our work in Azure Research has contributed to the standardization, development, and deployment of CXL over the past five years. In this talk, we share lessons learned and current expectations for realistic CXL deployments from the perspective of a major cloud platform. We review deployment steps such as CXL 1.1 local memory expansion, CXL 2.0/3.0 memory pools, and CXL 3.0/3.1+ memory sharing with back invalidate, and contrast them with timelines and hardware availability. We also comment on architectural and cost considerations that shed light on specific design questions such as pool sizes and sharing implementations.

Data, Storage, Memory, and Overall System Efficiency

Gustavo Alonso (ETH Zurich)

Many applications dominating the computing landscape are data intensive: data analytics, machine learning, large language models, recommendation systems, etc. The amount of data processed by these systems is staggering and continues to grow at an exponential rate. While the use of more and more data has led to impressive progress in many areas, including storage and memory systems, it has an often-ignored side effect: data movement is expensive, requires many resources, and it is often inefficiently managed. Any serious attempt at improving the sustainability and overall efficiency of data centers must necessarily include improvements in the way we handle and process data. In this talk I will first show comment on the environmental impact of current IT. Then I will discuss why existing systems are inherently inefficient in data movement, resource utilization, and processing requirements. I will then present potential solutions that take advantage of the trends towards specialization and the large economies of scale of the cloud, suggesting along the way how to design data centric architectures at the storage and memory level that are more energy and resource efficient than what we have today.